The present invention relates to a reading method and a circuit for a nonvolatile memory.
As is known, in a floating gate non-volatile memory cell storage of a logic state is carried out by programming the threshold voltage of the cell itself through the definition of the quantity of electrical charge stored in the floating gate region.
Reading of a memory cell is carried out using a read circuit known as xe2x80x9csense amplifier,xe2x80x9d which, in addition to recognizing the logic state stored in the memory cell, also provides for the correct biasing of the drain terminal of the memory cell.
FIG. 1 illustrates by way of example a known sense amplifier used to read multi-level flash memory cells.
The sense amplifier, indicated as a whole by 1, is a successive approximation sense amplifier comprising a supply line 2 set to the supply voltage VCC; a ground line 4 set to the ground voltage VGND; an array branch 6 connected via an array bit line 8 to a non-volatile memory cell 10, the content of which is to be read; a reference branch 12 connected via a reference bit line 14 to a digital/analog converter (DAC) 16, which draws at an output a reference current IR; a current/voltage converter stage 18 connected to the array and reference branches 6, 12 for converting the currents flowing in these branches respectively into an array potential VM and a reference potential VR; a differential comparator stage 20 for comparing the array and reference potentials VM and VR and supplying at an output a logic comparison signal COMP indicative of the result of the comparison; and an n-bit successive approximation register (SAR) 22, wherein n is the number of bits stored in the memory cell 10, having an input connected to the output of the comparator stage 20, and a plurality n of outputs connected to respective inputs of the digital/analogue converter 16, for driving the digital/analogue converter 16 in order to vary the reference current IR required by the converter at the output, in the manner described in detail hereinafter.
In the example illustrated, the memory cell 10 to be read is a multi-level memory cell in which four bits (16 levels) are stored, and has a gate terminal receiving a reading signal VREAD, a drain terminal connected to the array bit line 8, and a source terminal connected to the ground line 4.
In the example illustrated, the successive approximation register 22 is consequently a four-bit register, and has four outputs, each of which is associated with a respective bit, and at which it supplies four control signals, indicated as B3, B2, B1 and B0, assuming a logic level correlated to the logic value assumed by the corresponding bit.
The array branch 6 comprises an array biasing stage 24 for biasing the drain terminal of the memory cell 10 to a predetermined potential, typically 1V; and an array column decoding stage, for the sake of simplicity schematized in FIG. 1 by means of a switch 25, arranged between the array biasing stage 24 and the array bit line 8, and typically formed of three series-connected NMOS transistors (not shown) receiving respective column decoding signals at gate terminals.
In particular, the array biasing stage 24 has a negative feedback cascode structure formed of a NMOS transistor 26 and a logic inverter 28; the NMOS transistor 26 has a drain terminal connected to the current/voltage converter stage 18, a source terminal connected to the array bit line 8 and to the input terminal of the logic inverter 28, and a gate terminal connected to the output terminal of the logic inverter 28. With this configuration, the electrical potential of the drain terminal of the memory cell 10 is approximately equivalent to the threshold voltage of the logic inverter 28, at which potential, in other words, the logic inverter 28 switches from one logic level to the other.
The reference branch 12 comprises a reference biasing stage 30 altogether identical to the array biasing stage 24, and having a feedback cascode structure formed of an NMOS transistor 32 and a logic inverter 34; the NMOS transistor 32 has a drain terminal connected to the current/voltage converter stage 18, a source terminal connected to the reference bit line 14 and to the input terminal of the logic inverter 34, and a gate terminal connected to the output terminal of the logic inverter 34.
The reference branch 12 additionally comprises a reference column decoding stage (not shown), arranged between the reference biasing stage 30 and the reference bit line 14, formed of three series-connected NMOS transistors kept continually switched on (typically by connecting their gate terminals to the supply line 2), and having the purpose of making the structure of the reference branch 12 and the array branch 6 symmetrical with one another.
The current/voltage converter stage 18 is formed of a current mirror comprising a first diode-connected PMOS transistor 36 arranged on the array branch 6, and a second PMOS transistor 38 arranged on the reference branch 12; in particular, the PMOS transistors 36 and 38 have gate terminals connected to one another and to the drain terminal of the PMOS transistor 36, source terminals connected to the supply line 2, and drain terminals connected respectively to the drain terminals of the NMOS transistor 26 and the NMOS transistor 32, and defining respectively an array node 40 and a reference node 42, at which the aforementioned array potential VM and reference potential VR, respectively, are present and to which the two input terminals of the comparator stage 20 are connected.
The sense amplifier 1 operates as follows. When a constant reading voltage VREAD, having a value greater than the highest threshold voltage which can be programmed in the memory cell 10, is applied to the gate terminal of the memory cell 10, and provided that the drain terminal of the memory cell 10 is kept at a sufficiently low, constant value of approximately 1 V, the memory cell 10 works in the triode operating zone, and draws an array current IM which is inversely proportional to the threshold voltage programmed, i.e., the higher its threshold voltage, the lower the current flowing in it.
The array current IM is mirrored onto the reference node 42 by the PMOS transistors 36 and 38 of the current mirror 18, and in the reference node 42 the reference current IR drawn by the digital/analogue converter 16 is subtracted from this mirrored current.
The array potential VM and the reference potential VR of the array node 40 and the reference node 42, respectively, are thus correlated respectively to the array current IM, and to the difference between the reference current IR and the array current IM mirrored onto the reference branch 12, and these potentials are compared with one another by the comparator stage 20, which supplies at an output the comparison signal COMP, which assumes a first logic level if VM is greater than VR, and a second, low logic level, if VM is smaller than VR.
The comparison signal COMP is then supplied to the successive approximation register 22, which, on the basis of the logic level of this signal, modifies the logic level of the control signals B3-B0, by implementing a dichotomous algorithm, which is known and therefore described briefly hereinafter.
In particular, the successive approximation register 22 controls the digital/analogue converter 16 such as to vary by steps the reference current IR drawn by the converter on the basis of the logic level assumed by the comparison signal COMP. In detail, as soon as the gate terminal of the memory cell 10 is supplied with the reading signal VREAD, the successive approximation register 22 is controlled such as to set the control signal B3 to the high logic level (most significant bit set to xe2x80x9c1xe2x80x9d). Consequently, the digital/analogue converter 16 draws a reference current IR having a value equivalent to half the maximum value which it can supply (i.e., a value which is correlated to the weight of the most significant bit which has been set to xe2x80x9c1xe2x80x9d), and this current begins to flow in the reference branch 12.
If the reference current IR is lower than the array current IM mirrored onto the reference branch 12, the potential VR varies towards values which are greater than those of the array potential VM, and the logic level consequently assumed by the comparison signal COMP controls the successive approximation register 22 such as to set the control signal B2 also to the high logic level (second most significant bit set to xe2x80x9c1xe2x80x9d), whereas if the reference current IR is greater than the array current IM mirrored onto the reference branch 12, the potential VR varies towards values which are lower than those of the array potential VM, and the logic level consequently assumed by the comparison signal COMP controls the successive approximation register 22 such as to set the control signal B3 to the low logic level (most significant bit set to xe2x80x9c0xe2x80x9d), and the control signal B2 to the high logic level (second most significant bit set to xe2x80x9c1xe2x80x9d).
In the first case, the reference current IR drawn by the digital/analogue converter 16 is consequently incremented by a value equivalent to one quarter of the maximum value which can be supplied (i.e., by a value correlated to the weight of the second most significant bit which has been set to xe2x80x9c1xe2x80x9d), and thus in total it assumes a value equivalent to three quarters of the maximum current which can be supplied, whereas in the second case, the reference current IR drawn by the digital/analogue converter 16 assumes a value equivalent to one quarter of the maximum value which can be supplied.
The comparison is then carried out once more between the new values assumed by the array and reference potentials VM and VR, and consequently the logic level of the control signals B3-B0 is modified, and by proceeding in this manner with successive approximations, at each comparison step there is determination of the value of one of the four bits stored in the memory cell 10 (dichotomous algorithm), and therefore the four bits stored in the memory cell 10 are written in four steps into the successive approximation register 22.
The main disadvantage of the known sense amplifiers is their high current consumption, particularly when the memory cell to be read is blank, or has a low threshold voltage. In fact, in these cases, the high reading voltage VREAD supplied to the gate terminal of the memory cell to be read, together with the low threshold voltage of the memory cell, causes the current flowing in the memory cell itself to assume a rather high value, approximately 50 xcexcA, which, when multiplied by the number of sense amplifiers which generally operate simultaneously in order to carry out parallel reading of several memory cells, gives rise to overall consumption which in some applications can be unacceptable.
The considerations described above for successive approximation sense amplifiers dedicated to reading of multi-level memory cells, also apply equally well to sense amplifiers dedicated to reading of flash memory cells, in which a single bit is stored, and in which the reference current IR is constant and generated by means of a reference memory cell having a known content.
An embodiment of the present invention provides a reading method and circuit for a non-volatile memory, which permit reduction of current consumption, compared with that of reading circuits according to the known prior art.
The reading circuit includes having a first branch coupled to a first current generator; a second branch connected to a second current generator; a current/voltage converter connected to the first and second branches and supplying at a first and second node respectively a first and a second electrical potential, correlated to currents flowing respectively in the first and second branches; and a comparator having first and second inputs coupled respectively to the first and second nodes for comparing the first and second electrical potentials; a sample and hold circuit arranged between the first node and the comparator, the sample and hold circuit selectively operable to sample and hold the first potential; and a switch for switching off the first branch.
According to one aspect of the invention, the reading circuit is formed of an array branch coupled via an array bit line to an array memory cell, the content of which is to be read; a reference branch coupled via a reference bit line to a current generator stage, which supplies a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, which supplies at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage coupled to the array node and to the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.
According to another aspect of the invention, a reading circuit for a non-volatile memory is provided wherein the inventive principle on which the present invention is based is applied without any modification to sense amplifiers in which it is the reference current which is reflected onto the array branch. Accordingly, the sample and hold stage is positioned between the reference node and the input terminal of the comparator stage to which this reference node is connected, and a switch for switching off the reference branch is provided.
According to other aspects of the present invention, a reading method for a non-volatile memory is also provided, wherein the reading method is implemented by means of a reading circuit having a first branch in which a first current flows, and a second branch in which a second current flows. The reading method converting the first current into a first electrical potential; converting the second current into a second electrical potential; comparing said first and second electrical potentials; sampling and holding the first electrical potential; and switching off the first branch of the reading circuit.
According to one aspect of the method of the invention, the first branch is an array branch and the second branch is a reference branch.
According to another aspect of the invention, the method for a reading circuit is implemented by means of a reading circuit also having a memory cell connected to the first branch, wherein the switching off the first branch of the reading circuit also includes switching off the memory cell.
According to yet another aspect of the invention, the method also includes zeroing a reading voltage supplied to a gate terminal of the memory cell.